1. Field of the Invention
The invention is related to data processing and, more particularly, to a method and apparatus for packet error detection on a PCI Express Bus link.
2. Description of the Prior Art
Data transfer over PCI express bus link interface is based on data packets. Two packet formats, TLP (transaction layer packet) and DLLP (data link layer packet), are defined in the PCI express bus specification. A receiver of a PCI express bus link should identify packet format, and accordingly perform the processes of receiving, buffering and transferring data.
FIGS. 1A and 1B respectively illustrate packet formats of TLP and DLLP defined in the PCI express bus specification. As shown in FIG 1A, a TLP packet has 1-byte start framing symbol 111, 2-byte sequence number 112, 3 or 4-doubleword header 113, 0˜4 Kbyte data 114 (should be multiple of 4), 8-byte CRC data 115 and 1-byte end framing symbol 116. As shown in FIG. 1B, a DLLP packet has 1-byte start framing symbol 121, 4-byte data 122, 2-byte CRC data 123 and 1-byte end framing symbol 124.
There is no error detection defined in the PCI express bus specification, it is assumed that all packets are correctly received when the transceiver of a PCI express bus link transmits packets. Packet error detection mechanism at receiver of the PCI express bus link is thus required to prevent unpredictable errors.